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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2/] [ChangeLog] - Rev 838

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123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5165d 10h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
122 Added l.ror and l.rori with associated tests. jeremybennett 5166d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5166d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5167d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5169d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5170d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5170d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5171d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
110 or1ksim make check should work without a libc in the or32-elf tools julius 5172d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5174d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/ChangeLog

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