OpenCores

URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2] - Rev 235

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5149d 14h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5150d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5152d 14h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
106	Removing old tests, pending addition of new ones.	jeremybennett	5152d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
104	Candidate release 0.4.0rc4	jeremybennett	5155d 22h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5164d 16h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
100	Single precision FPU stuff for or1ksim	julius	5164d 18h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
99	Bug in test evaluation for library fixed.	jeremybennett	5169d 16h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5170d 17h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5184d 23h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.