URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 508

Rev	Log message	Author	Age	Path
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	4887d 16h	/openrisc/trunk
487	ORPSoC main software makefile update	julius	4890d 14h	/openrisc/trunk
486	ORPSoC updates, mainly software, i2c driver	julius	4890d 14h	/openrisc/trunk
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4894d 18h	/openrisc/trunk
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4895d 16h	/openrisc/trunk
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4897d 19h	/openrisc/trunk
482	Don't hardcode tool versions in help text	olof	4899d 07h	/openrisc/trunk
481	OR1200 Update. RTL and spec.	julius	4911d 01h	/openrisc/trunk
480	ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.	julius	4911d 23h	/openrisc/trunk
479	ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.	julius	4912d 22h	/openrisc/trunk