URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] - Rev 513

Rev	Log message	Author	Age	Path
490	Updates to fix spurious test failures and register scheduling.	jeremybennett	4891d 13h	/openrisc/trunk
489	ORPSoC sw cleanup. Remove warnings.	julius	4896d 19h	/openrisc/trunk
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	4896d 20h	/openrisc/trunk
487	ORPSoC main software makefile update	julius	4899d 18h	/openrisc/trunk
486	ORPSoC updates, mainly software, i2c driver	julius	4899d 18h	/openrisc/trunk
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4903d 22h	/openrisc/trunk
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4904d 20h	/openrisc/trunk
483	Updated with new opcodes to generate random numbers and to identify us as Or1ksim.	jeremybennett	4906d 22h	/openrisc/trunk
482	Don't hardcode tool versions in help text	olof	4908d 11h	/openrisc/trunk
481	OR1200 Update. RTL and spec.	julius	4920d 05h	/openrisc/trunk