URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 236

Rev	Log message	Author	Age	Path
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5141d 05h	/openrisc/trunk/or1ksim
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5142d 03h	/openrisc/trunk/or1ksim
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5143d 05h	/openrisc/trunk/or1ksim
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5145d 04h	/openrisc/trunk/or1ksim
106	Removing old tests, pending addition of new ones.	jeremybennett	5145d 04h	/openrisc/trunk/or1ksim
104	Candidate release 0.4.0rc4	jeremybennett	5148d 11h	/openrisc/trunk/or1ksim
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5157d 05h	/openrisc/trunk/or1ksim
100	Single precision FPU stuff for or1ksim	julius	5157d 08h	/openrisc/trunk/or1ksim
99	Bug in test evaluation for library fixed.	jeremybennett	5162d 05h	/openrisc/trunk/or1ksim
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5163d 07h	/openrisc/trunk/or1ksim