URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] - Rev 616

Rev	Log message	Author	Age	Path
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5025d 14h	/openrisc/trunk/or1ksim
440	Updated documentation to describe new Ethernet usage.	jeremybennett	5026d 15h	/openrisc/trunk/or1ksim
437	Or1ksim - ethernet peripheral update, working much better.	julius	5034d 10h	/openrisc/trunk/or1ksim
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5035d 10h	/openrisc/trunk/or1ksim
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	5038d 16h	/openrisc/trunk/or1ksim
433	New single program interrupt test programs.	jeremybennett	5039d 19h	/openrisc/trunk/or1ksim
432	Updates to handle interrupts correctly.	jeremybennett	5039d 20h	/openrisc/trunk/or1ksim
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	5042d 16h	/openrisc/trunk/or1ksim
429	or1ksim update - remove debug printfs from eth MDIO emulation function and fix illegal instruction vector jump for invalid instructions.	julius	5042d 20h	/openrisc/trunk/or1ksim
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	5045d 15h	/openrisc/trunk/or1ksim