OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [configure] - Rev 309

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
104 Candidate release 0.4.0rc4 jeremybennett 5147d 08h /openrisc/trunk/or1ksim/configure
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5156d 01h /openrisc/trunk/or1ksim/configure
99 Bug in test evaluation for library fixed. jeremybennett 5161d 02h /openrisc/trunk/or1ksim/configure
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5162d 03h /openrisc/trunk/or1ksim/configure
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5176d 09h /openrisc/trunk/or1ksim/configure
96 Various changes which had not been picked up in earlier commits. jeremybennett 5177d 10h /openrisc/trunk/or1ksim/configure
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5183d 01h /openrisc/trunk/or1ksim/configure
91 Tidy up of some obsolete configuration code. jeremybennett 5189d 23h /openrisc/trunk/or1ksim/configure
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5190d 00h /openrisc/trunk/or1ksim/configure
89 Tidy up for latest bug fixes. jeremybennett 5190d 07h /openrisc/trunk/or1ksim/configure

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.