URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] - Rev 230

Rev	Log message	Author	Age	Path
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5153d 00h	/openrisc/trunk/or1ksim/cpu
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5167d 06h	/openrisc/trunk/or1ksim/cpu
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5168d 07h	/openrisc/trunk/or1ksim/cpu
91	Tidy up of some obsolete configuration code.	jeremybennett	5180d 20h	/openrisc/trunk/or1ksim/cpu
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5180d 21h	/openrisc/trunk/or1ksim/cpu
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5181d 21h	/openrisc/trunk/or1ksim/cpu
80	Add missing configuration files to SVN.	jeremybennett	5182d 00h	/openrisc/trunk/or1ksim/cpu
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5512d 06h	/openrisc/trunk/or1ksim/cpu