URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu] - Rev 239

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5181d 20h	/openrisc/trunk/or1ksim/cpu
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5184d 21h	/openrisc/trunk/or1ksim/cpu
104	Candidate release 0.4.0rc4	jeremybennett	5188d 04h	/openrisc/trunk/or1ksim/cpu
101	ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c	jeremybennett	5196d 22h	/openrisc/trunk/or1ksim/cpu
100	Single precision FPU stuff for or1ksim	julius	5197d 00h	/openrisc/trunk/or1ksim/cpu
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5202d 23h	/openrisc/trunk/or1ksim/cpu
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5217d 05h	/openrisc/trunk/or1ksim/cpu
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5218d 07h	/openrisc/trunk/or1ksim/cpu
91	Tidy up of some obsolete configuration code.	jeremybennett	5230d 20h	/openrisc/trunk/or1ksim/cpu
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5230d 21h	/openrisc/trunk/or1ksim/cpu