OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.info] - Rev 403

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5125d 08h	/openrisc/trunk/or1ksim/doc/or1ksim.info
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5126d 09h	/openrisc/trunk/or1ksim/doc/or1ksim.info
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5128d 09h	/openrisc/trunk/or1ksim/doc/or1ksim.info
104	Candidate release 0.4.0rc4	jeremybennett	5131d 16h	/openrisc/trunk/or1ksim/doc/or1ksim.info
100	Single precision FPU stuff for or1ksim	julius	5140d 12h	/openrisc/trunk/or1ksim/doc/or1ksim.info
99	Bug in test evaluation for library fixed.	jeremybennett	5145d 10h	/openrisc/trunk/or1ksim/doc/or1ksim.info
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5146d 11h	/openrisc/trunk/or1ksim/doc/or1ksim.info
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5161d 18h	/openrisc/trunk/or1ksim/doc/or1ksim.info
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5167d 09h	/openrisc/trunk/or1ksim/doc/or1ksim.info
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5174d 09h	/openrisc/trunk/or1ksim/doc/or1ksim.info

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.