URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 400

Rev	Log message	Author	Age	Path
350	Adding new OR1200 processor to ORPSoCv2	julius	5075d 11h	/openrisc/trunk/orpsocv2
349	ORPSoCv2 update with new software and makefile update	julius	5075d 11h	/openrisc/trunk/orpsocv2
348	First stage of ORPSoCv2 update - more to come	julius	5075d 11h	/openrisc/trunk/orpsocv2
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5133d 10h	/openrisc/trunk/orpsocv2
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5165d 11h	/openrisc/trunk/orpsocv2
78	Fixed typo in Silos workaround script	rherveille	5228d 06h	/openrisc/trunk/orpsocv2
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5228d 07h	/openrisc/trunk/orpsocv2
76	Added: +libext+.v Added: +incdir+.	rherveille	5229d 06h	/openrisc/trunk/orpsocv2
71	ORPSoC board builds, adding readmes	julius	5271d 16h	/openrisc/trunk/orpsocv2
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5275d 21h	/openrisc/trunk/orpsocv2