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[/] [openrisc/] [trunk/] [orpsocv2/] - Rev 530

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480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4906d 23h /openrisc/trunk/orpsocv2
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4907d 22h /openrisc/trunk/orpsocv2
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4909d 14h /openrisc/trunk/orpsocv2
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4909d 22h /openrisc/trunk/orpsocv2
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4910d 15h /openrisc/trunk/orpsocv2
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4910d 18h /openrisc/trunk/orpsocv2
470 ORPSoC OR1200 crt0 updates. julius 4914d 18h /openrisc/trunk/orpsocv2
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI		 julius 4915d 19h /openrisc/trunk/orpsocv2
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README		 julius 4916d 22h /openrisc/trunk/orpsocv2
465 ORPSoC SPI flash load Makefile and README updates. julius 4917d 12h /openrisc/trunk/orpsocv2

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