URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 412

Rev	Log message	Author	Age	Path
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5382d 00h	/openrisc/trunk/orpsocv2/bench
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5382d 20h	/openrisc/trunk/orpsocv2/bench
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5396d 22h	/openrisc/trunk/orpsocv2/bench
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5415d 16h	/openrisc/trunk/orpsocv2/bench
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5431d 03h	/openrisc/trunk/orpsocv2/bench
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5467d 02h	/openrisc/trunk/orpsocv2/bench
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5506d 20h	/openrisc/trunk/orpsocv2/bench
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5511d 03h	/openrisc/trunk/orpsocv2/bench
6	Checking in ORPSoCv2	julius	5529d 15h	/openrisc/trunk/orpsocv2/bench