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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 568

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67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5289d 22h /openrisc/trunk/orpsocv2/bench/verilog
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5314d 02h /openrisc/trunk/orpsocv2/bench/verilog
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5373d 18h /openrisc/trunk/orpsocv2/bench/verilog
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5384d 10h /openrisc/trunk/orpsocv2/bench/verilog
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5427d 16h /openrisc/trunk/orpsocv2/bench/verilog
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5446d 10h /openrisc/trunk/orpsocv2/bench/verilog
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5461d 21h /openrisc/trunk/orpsocv2/bench/verilog
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5497d 21h /openrisc/trunk/orpsocv2/bench/verilog
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5541d 21h /openrisc/trunk/orpsocv2/bench/verilog
6 Checking in ORPSoCv2 julius 5560d 09h /openrisc/trunk/orpsocv2/bench/verilog

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