URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 477

Rev	Log message	Author	Age	Path
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5428d 01h	/openrisc/trunk/orpsocv2/bench/verilog
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5446d 19h	/openrisc/trunk/orpsocv2/bench/verilog
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5462d 06h	/openrisc/trunk/orpsocv2/bench/verilog
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5498d 05h	/openrisc/trunk/orpsocv2/bench/verilog
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5542d 06h	/openrisc/trunk/orpsocv2/bench/verilog
6	Checking in ORPSoCv2	julius	5560d 18h	/openrisc/trunk/orpsocv2/bench/verilog