URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 397

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5328d 23h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5339d 06h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5357d 07h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5372d 05h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5390d 23h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5442d 09h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5466d 06h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5482d 03h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5486d 10h	/openrisc/trunk/orpsocv2/sim/bin/Makefile
36	Better clean rule in makefile	julius	5500d 10h	/openrisc/trunk/orpsocv2/sim/bin/Makefile