OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 435

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5277d 22h /openrisc/trunk/orpsocv2/sim/bin/Makefile
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5287d 19h /openrisc/trunk/orpsocv2/sim/bin/Makefile
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5329d 15h /openrisc/trunk/orpsocv2/sim/bin/Makefile
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5334d 19h /openrisc/trunk/orpsocv2/sim/bin/Makefile
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5345d 12h /openrisc/trunk/orpsocv2/sim/bin/Makefile
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5355d 19h /openrisc/trunk/orpsocv2/sim/bin/Makefile
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5373d 19h /openrisc/trunk/orpsocv2/sim/bin/Makefile
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5388d 18h /openrisc/trunk/orpsocv2/sim/bin/Makefile
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5407d 12h /openrisc/trunk/orpsocv2/sim/bin/Makefile
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5458d 22h /openrisc/trunk/orpsocv2/sim/bin/Makefile

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.