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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Rev 630

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351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5042d 12h /openrisc/trunk/orpsocv2/sim/bin/Makefile
348 First stage of ORPSoCv2 update - more to come julius 5042d 16h /openrisc/trunk/orpsocv2/sim/bin/Makefile
78 Fixed typo in Silos workaround script rherveille 5195d 11h /openrisc/trunk/orpsocv2/sim/bin/Makefile
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5195d 12h /openrisc/trunk/orpsocv2/sim/bin/Makefile
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5243d 02h /openrisc/trunk/orpsocv2/sim/bin/Makefile
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5243d 03h /openrisc/trunk/orpsocv2/sim/bin/Makefile
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5245d 18h /openrisc/trunk/orpsocv2/sim/bin/Makefile
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5245d 21h /openrisc/trunk/orpsocv2/sim/bin/Makefile
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5265d 19h /openrisc/trunk/orpsocv2/sim/bin/Makefile
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5272d 20h /openrisc/trunk/orpsocv2/sim/bin/Makefile

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