URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sim] - Rev 356

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5418d 15h	/openrisc/trunk/orpsocv2/sim
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5470d 02h	/openrisc/trunk/orpsocv2/sim
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5493d 23h	/openrisc/trunk/orpsocv2/sim
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5509d 20h	/openrisc/trunk/orpsocv2/sim
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5514d 02h	/openrisc/trunk/orpsocv2/sim
36	Better clean rule in makefile	julius	5528d 03h	/openrisc/trunk/orpsocv2/sim
6	Checking in ORPSoCv2	julius	5532d 14h	/openrisc/trunk/orpsocv2/sim