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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] - Rev 412

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Rev Log message Author Age Path
349 ORPSoCv2 update with new software and makefile update julius 5061d 03h /openrisc/trunk/orpsocv2/sw
348 First stage of ORPSoCv2 update - more to come julius 5061d 03h /openrisc/trunk/orpsocv2/sw
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5264d 07h /openrisc/trunk/orpsocv2/sw
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5284d 05h /openrisc/trunk/orpsocv2/sw
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5301d 04h /openrisc/trunk/orpsocv2/sw
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5343d 00h /openrisc/trunk/orpsocv2/sw
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5402d 02h /openrisc/trunk/orpsocv2/sw
50 Adding or32_funcs.S julius 5402d 06h /openrisc/trunk/orpsocv2/sw
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5420d 20h /openrisc/trunk/orpsocv2/sw
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5436d 07h /openrisc/trunk/orpsocv2/sw

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