URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2] - Rev 353

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5347d 08h	/openrisc/trunk/orpsocv2
56	adding generic pll model to orpsoc	julius	5355d 11h	/openrisc/trunk/orpsocv2
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5358d 01h	/openrisc/trunk/orpsocv2
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5368d 08h	/openrisc/trunk/orpsocv2
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5386d 09h	/openrisc/trunk/orpsocv2
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5387d 05h	/openrisc/trunk/orpsocv2
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5401d 07h	/openrisc/trunk/orpsocv2
50	Adding or32_funcs.S	julius	5401d 11h	/openrisc/trunk/orpsocv2
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5420d 01h	/openrisc/trunk/orpsocv2
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5435d 12h	/openrisc/trunk/orpsocv2