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[/] [openrisc/] [trunk/] [orpsocv2] - Rev 364

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69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5289d 19h /openrisc/trunk/orpsocv2
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5292d 11h /openrisc/trunk/orpsocv2
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5292d 14h /openrisc/trunk/orpsocv2
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5312d 12h /openrisc/trunk/orpsocv2
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5316d 18h /openrisc/trunk/orpsocv2
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5319d 13h /openrisc/trunk/orpsocv2
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5329d 10h /openrisc/trunk/orpsocv2
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5371d 06h /openrisc/trunk/orpsocv2
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5376d 10h /openrisc/trunk/orpsocv2
56 adding generic pll model to orpsoc julius 5384d 12h /openrisc/trunk/orpsocv2

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