URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2] - Rev 395

Rev	Log message	Author	Age	Path
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5118d 03h	/openrisc/trunk/orpsocv2
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5150d 04h	/openrisc/trunk/orpsocv2
78	Fixed typo in Silos workaround script	rherveille	5213d 00h	/openrisc/trunk/orpsocv2
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5213d 00h	/openrisc/trunk/orpsocv2
76	Added: +libext+.v Added: +incdir+.	rherveille	5213d 23h	/openrisc/trunk/orpsocv2
71	ORPSoC board builds, adding readmes	julius	5256d 09h	/openrisc/trunk/orpsocv2
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5260d 14h	/openrisc/trunk/orpsocv2
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5260d 15h	/openrisc/trunk/orpsocv2
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5263d 06h	/openrisc/trunk/orpsocv2
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5263d 09h	/openrisc/trunk/orpsocv2