URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk] - Rev 206

Rev	Log message	Author	Age	Path
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5101d 21h	/openrisc/trunk
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5101d 21h	/openrisc/trunk
184	Fix the UART version of newlib.	jeremybennett	5103d 01h	/openrisc/trunk
183	Fix to setjmp, so it works. Some commenting tidy ups elsewhere.	jeremybennett	5103d 17h	/openrisc/trunk
182	Removed redundant code.	jeremybennett	5103d 18h	/openrisc/trunk
181	Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed.	jeremybennett	5103d 20h	/openrisc/trunk
180	Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART.	jeremybennett	5103d 20h	/openrisc/trunk
179	Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors.	jeremybennett	5103d 20h	/openrisc/trunk
178	Fixes a bug in prologue recognition without frame pointer.	jeremybennett	5103d 20h	/openrisc/trunk
177	Specified CPU type for or32, corrected templates for or32--elf. Corrected specs in or32.h, added init and fini. Added support for newlib, including -mor32-newlib and -mor32-newlib-uart options.	jeremybennett	5103d 20h	/openrisc/trunk