URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk] - Rev 466

Rev	Log message	Author	Age	Path
446	gdb-7.2 gdbserver updates.	julius	4966d 18h	/openrisc/trunk
445	gdbserver update to use kernel port ptrace register definitions.	julius	4967d 15h	/openrisc/trunk
444	Changes to ABI handling of varargs.	jeremybennett	4968d 00h	/openrisc/trunk
443	Work in progress on more efficient Ethernet.	jeremybennett	4968d 03h	/openrisc/trunk
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4968d 17h	/openrisc/trunk
441	Changes for gdbserver.	jeremybennett	4969d 00h	/openrisc/trunk
440	Updated documentation to describe new Ethernet usage.	jeremybennett	4969d 19h	/openrisc/trunk
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4971d 23h	/openrisc/trunk
438	Fix to newlib header and library locations.	jeremybennett	4975d 00h	/openrisc/trunk
437	Or1ksim - ethernet peripheral update, working much better.	julius	4977d 13h	/openrisc/trunk