URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc] - Rev 133

Rev	Log message	Author	Age	Path
113	Updates to exception handling for l.add and l.div	jeremybennett	5175d 08h	/openrisc
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5175d 08h	/openrisc
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5175d 13h	/openrisc
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5176d 10h	/openrisc
109	or_debug_proxy does signals with signals, just ignores signals	julius	5176d 18h	/openrisc
108	Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu.	jeremybennett	5178d 08h	/openrisc
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5178d 09h	/openrisc
106	Removing old tests, pending addition of new ones.	jeremybennett	5178d 09h	/openrisc
105	Tagging the 0.4.0rc1 candidate release of Or1ksim	jeremybennett	5181d 16h	/openrisc
104	Candidate release 0.4.0rc4	jeremybennett	5181d 16h	/openrisc