URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc] - Rev 140

Rev	Log message	Author	Age	Path
120	Documents exception generation by l.jalr and l.jr	jeremybennett	5193d 11h	/openrisc
119	Updated to clarify exceptions for division and details of multiplication.	jeremybennett	5193d 23h	/openrisc
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5194d 08h	/openrisc
117	Updates on l.ff1, l.fl1 and l.maci.	jeremybennett	5196d 11h	/openrisc
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5196d 11h	/openrisc
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5197d 11h	/openrisc
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5197d 12h	/openrisc
113	Updates to exception handling for l.add and l.div	jeremybennett	5198d 11h	/openrisc
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5198d 11h	/openrisc
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5198d 16h	/openrisc