URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc] - Rev 531

Rev	Log message	Author	Age	Path
511	Tagging the 0.5.1rc1 release of Or1ksim	jeremybennett	4842d 19h	/openrisc
510	Updates for release 0.5.1rc1.	jeremybennett	4842d 19h	/openrisc
509	Tagging the 0.5.0rc3 release of Or1ksim	jeremybennett	4842d 20h	/openrisc
508	Updates for Or1ksim 0.5.0rc3.	jeremybennett	4843d 19h	/openrisc
507	Newlib libgloss board support update. Corresponding GCC port changes to support it.	julius	4849d 16h	/openrisc
506	ORPSoC or1200 interrupt and syscall generation test	julius	4850d 15h	/openrisc
505	OR1200 overflow detection fixup SPIflash program update or1200 driver library timer improvement	julius	4850d 16h	/openrisc
504	ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup	julius	4867d 12h	/openrisc
503	ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers.	julius	4868d 08h	/openrisc
502	ORPSoC update - or1200, ethmac Xilinx fifos or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default	julius	4870d 12h	/openrisc