URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc] - Rev 69

Rev	Log message	Author	Age	Path
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5442d 17h	/openrisc
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5442d 20h	/openrisc
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5452d 04h	/openrisc
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5458d 04h	/openrisc
45	Orpsoc eth test fix and script error message update	julius	5465d 04h	/openrisc
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5494d 04h	/openrisc
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5518d 01h	/openrisc
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5533d 22h	/openrisc
41	Update to or1k top	julius	5536d 23h	/openrisc
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5538d 04h	/openrisc