URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc] - Rev 214

Rev	Log message	Author	Age	Path
194	Tidied up code setjmp and longjmp into their own files, and adjusted Makefile accordingly. Simplified cache setup in startup code. Replaced calls via register with calls using immediate address.	jeremybennett	5145d 13h	/openrisc
193	Record changes to initfini.c	jeremybennett	5145d 13h	/openrisc
192	Updated to fix problems with initfini assembler fragments.	jeremybennett	5145d 13h	/openrisc
191	Updated to clarify use of r9 in the l.jalr delay slot.	jeremybennett	5145d 14h	/openrisc
190	Allow the Or1ksim installation directory to be set by option.	jeremybennett	5145d 20h	/openrisc
189	Fuller explanation of the build script given.	jeremybennett	5145d 20h	/openrisc
188	More rigorous testing of options.	jeremybennett	5145d 20h	/openrisc
187	Or1200 sprs FPU update	julius	5147d 13h	/openrisc
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5147d 16h	/openrisc
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5147d 17h	/openrisc