URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc] - Rev 75

Rev	Log message	Author	Age	Path
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5384d 22h	/openrisc
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5395d 05h	/openrisc
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5413d 06h	/openrisc
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5414d 02h	/openrisc
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5428d 04h	/openrisc
50	Adding or32_funcs.S	julius	5428d 09h	/openrisc
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5446d 22h	/openrisc
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5447d 01h	/openrisc
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5456d 09h	/openrisc
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5462d 10h	/openrisc