OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc] - Rev 88

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5324d 18h /openrisc
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5324d 21h /openrisc
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5344d 19h /openrisc
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5349d 01h /openrisc
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5351d 20h /openrisc
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5361d 17h /openrisc
62 This material is part of the separate website downloads directory. jeremybennett 5372d 20h /openrisc
61 The build directory should not be part of the SVN configuration. jeremybennett 5372d 21h /openrisc
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5379d 14h /openrisc
59 Toolchain install script gcc patch change and gdb configure change julius 5400d 14h /openrisc

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.