URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [hello-uart_v1_0/] - Rev 1780

Rev	Log message	Author	Age	Path
1192	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7589d 00h	/or1k/tags/hello-uart_v1_0
1191	disabled 'bench_defines.v' during synthesis + added define to specify usage of flash instruction address	dries	7589d 00h	/or1k/tags/hello-uart_v1_0
1188	Added support for rams with byte write access.	simons	7604d 23h	/or1k/tags/hello-uart_v1_0
1186	Added support for rams with byte write access.	simons	7605d 22h	/or1k/tags/hello-uart_v1_0
1184	Scan signals mess fixed.	simons	7612d 15h	/or1k/tags/hello-uart_v1_0
1183	OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0	sfurman	7617d 07h	/or1k/tags/hello-uart_v1_0
1181	Initial import of unmodified gdb-5.3 source on vendor branch	sfurman	7617d 09h	/or1k/tags/hello-uart_v1_0
1179	BIST interface added for Artisan memory instances.	simons	7620d 18h	/or1k/tags/hello-uart_v1_0
1178	avoid another immu exception that should not happen	phoenix	7650d 06h	/or1k/tags/hello-uart_v1_0
1177	more informative output	phoenix	7651d 12h	/or1k/tags/hello-uart_v1_0