OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [common/] - Rev 1782

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1244 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.
hpanther 7480d 10h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7484d 20h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1218 segfault when there is no memory context fix phoenix 7532d 23h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1150 remove unneded include phoenix 7777d 10h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1117 Ignore generated files for CVS purposes sfurman 7821d 01h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1061 ELF sym loading improved markom 7961d 10h /or1k/tags/nog_patch_47/or1ksim/cpu/common
1049 Added "breaks" command that prints all set breakpoints. ivang 7988d 08h /or1k/tags/nog_patch_47/or1ksim/cpu/common
997 PRINTF should be used instead of printf; command redirection repaired markom 8009d 16h /or1k/tags/nog_patch_47/or1ksim/cpu/common
992 A bug when cache enabled and bus error comes fixed. simons 8011d 07h /or1k/tags/nog_patch_47/or1ksim/cpu/common
970 Testbench is now running on ORP architecture platform. simons 8017d 03h /or1k/tags/nog_patch_47/or1ksim/cpu/common

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.