URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [cpu/] [common/] [abstract.c] - Rev 1778

Rev	Log message	Author	Age	Path
970	Testbench is now running on ORP architecture platform.	simons	8000d 16h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
897	improved CUC GUI; pre/unroll bugs fixed	markom	8029d 21h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
884	code cleaning - a lot of global variables moved to runtime struct	markom	8037d 03h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
882	Routine for adjusting read and write delay for devices added.	simons	8040d 01h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
860	Added delayr and delayw variable initialization (default value 1)	ivang	8084d 15h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
638	TLBTR CI bit is now working properly.	simons	8195d 17h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
631	Real cache access is simulated now.	simons	8198d 16h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
611	EEAR register is not changed by trap, sys, int, tick and range exception.	simons	8205d 06h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
599	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8208d 15h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c
587	gdb messages disabled	markom	8210d 22h	/or1k/tags/nog_patch_61/or1ksim/cpu/common/abstract.c