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Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [dmmu.c] - Rev 1780

Rev	Log message	Author	Age	Path
438	ITLB -> DTLB lapsus fixed.	simons	8226d 15h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
430	dpfault and ipfault exceptions implemented	markom	8227d 14h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
429	cache configuration added	markom	8227d 15h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
425	immu and dmmu configurations added	markom	8227d 17h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
344	added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model	markom	8254d 18h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8352d 15h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8435d 01h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8641d 22h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
62	OR1K DMMU model.	lampret	8653d 22h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8876d 08h	/or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c