OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_62/] [or1ksim/] [cpu/] [or1k/] [except.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
437 When lsu instruction produce exception registers are preserved. simons 8311d 06h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8339d 08h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8351d 10h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
254 Made error report more verbose erez 8353d 05h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8360d 09h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
182 updated exception handling procedures chris 8408d 13h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed
markom 8437d 05h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
152 Breakpoint exceptions from single step are not printed now. chris 8479d 13h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
139 Modifications for functional gdb chris 8481d 08h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c
133 moved header files to match other utilities
repaired l.sra and some other shifting instructions
started build_automata for binary instruction decode
markom 8487d 09h /or1k/tags/nog_patch_62/or1ksim/cpu/or1k/except.c

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.