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Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_68/] [or1ksim/] [cpu/] [common/] [abstract.c] - Rev 1765

Rev	Log message	Author	Age	Path
992	A bug when cache enabled and bus error comes fixed.	simons	8013d 11h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
970	Testbench is now running on ORP architecture platform.	simons	8019d 07h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
897	improved CUC GUI; pre/unroll bugs fixed	markom	8048d 12h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
884	code cleaning - a lot of global variables moved to runtime struct	markom	8055d 18h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
882	Routine for adjusting read and write delay for devices added.	simons	8058d 16h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
860	Added delayr and delayw variable initialization (default value 1)	ivang	8103d 06h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
638	TLBTR CI bit is now working properly.	simons	8214d 08h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
631	Real cache access is simulated now.	simons	8217d 07h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
611	EEAR register is not changed by trap, sys, int, tick and range exception.	simons	8223d 21h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c
599	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8227d 06h	/or1k/tags/nog_patch_68/or1ksim/cpu/common/abstract.c