OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [sim.cfg] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1126 Added lengthy comment explaining all possible choices for UART
channels, e.g. xterm, tcp, file, etc.
sfurman 7764d 18h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
1076 channels integration rprescott 7915d 20h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
1021 *** empty log message *** rherveille 7973d 21h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
897 improved CUC GUI; pre/unroll bugs fixed markom 8018d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
883 cuc updated, cuc prompt parsing; CSM analysis markom 8026d 02h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
879 Initial version of OpenRISC Custom Unit Compiler added markom 8031d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
876 Beta release of ATA simulation rherveille 8032d 18h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
730 tick section is now obsolete; update your .cfg files! markom 8150d 06h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
725 Added some more configuration parameters. ivang 8151d 02h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg
724 Configuration of ethernet model socket interface and IRQ added. ivang 8151d 02h /or1k/tags/rel-0-3-0-rc1/or1ksim/sim.cfg

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.