OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cpu/] [or32] - Rev 604

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
482 profiling uses l.jr instead of obsolete l.jalr markom 8242d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
479 connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed markom 8242d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
464 Some small bugs fixed. simons 8243d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
458 Align, bus error and range exception fixed. simons 8244d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
437 When lsu instruction produce exception registers are preserved. simons 8249d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
431 stepping over breakpoint added markom 8249d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
416 IMMU bugs fixed. simons 8253d 03h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
394 dependency joined with dependstats; history moved to sim section markom 8263d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
393 messages: exception on many places changed to abort markom 8263d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
389 Changed default delay for load and store in superscalar cpu. lampret 8264d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.