URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog] - Rev 573

Rev	Log message	Author	Age	Path
359	Added optional sampling of inputs.	lampret	8270d 10h	/or1k/tags/rel_1/or1200/rtl/verilog
358	Fixed virtual silicon single-port rams instantiation.	lampret	8270d 10h	/or1k/tags/rel_1/or1200/rtl/verilog
357	Fixed dbg_is_o assignment width.	lampret	8270d 10h	/or1k/tags/rel_1/or1200/rtl/verilog
356	Break point bug fixed	simons	8270d 13h	/or1k/tags/rel_1/or1200/rtl/verilog
354	Fixed width of du_except.	lampret	8271d 06h	/or1k/tags/rel_1/or1200/rtl/verilog
353	Cashes disabled.	simons	8271d 17h	/or1k/tags/rel_1/or1200/rtl/verilog
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8272d 20h	/or1k/tags/rel_1/or1200/rtl/verilog
351	Fixed some l.trap typos.	lampret	8272d 21h	/or1k/tags/rel_1/or1200/rtl/verilog
350	For GDB changed single stepping and disabled trap exception.	lampret	8272d 23h	/or1k/tags/rel_1/or1200/rtl/verilog
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8277d 21h	/or1k/tags/rel_1/or1200/rtl/verilog