OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] [or1200] - Rev 1083

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7996d 23h /or1k/tags/rel_12/or1200
993 Fixed IMMU bug. lampret 7996d 23h /or1k/tags/rel_12/or1200
984 Disable SB until it is tested lampret 8000d 04h /or1k/tags/rel_12/or1200
977 Added store buffer. lampret 8000d 06h /or1k/tags/rel_12/or1200
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8003d 19h /or1k/tags/rel_12/or1200
960 Directory cleanup. lampret 8003d 20h /or1k/tags/rel_12/or1200
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8004d 19h /or1k/tags/rel_12/or1200
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8006d 20h /or1k/tags/rel_12/or1200
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8006d 20h /or1k/tags/rel_12/or1200
942 Delayed external access at page crossing. lampret 8006d 20h /or1k/tags/rel_12/or1200

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.