URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] [or1200] - Rev 1130

Rev	Log message	Author	Age	Path
1032	Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.	lampret	7980d 20h	/or1k/tags/rel_12/or1200
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	7984d 01h	/or1k/tags/rel_12/or1200
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	7984d 04h	/or1k/tags/rel_12/or1200
1011	Removed some commented RTL. Fixed SR/ESR flag bug.	lampret	7991d 00h	/or1k/tags/rel_12/or1200
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7997d 00h	/or1k/tags/rel_12/or1200
993	Fixed IMMU bug.	lampret	7997d 00h	/or1k/tags/rel_12/or1200
984	Disable SB until it is tested	lampret	8000d 04h	/or1k/tags/rel_12/or1200
977	Added store buffer.	lampret	8000d 06h	/or1k/tags/rel_12/or1200
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8003d 20h	/or1k/tags/rel_12/or1200
960	Directory cleanup.	lampret	8003d 20h	/or1k/tags/rel_12/or1200