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[/] [or1k/] [tags/] [rel_14/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1765

Rev	Log message	Author	Age	Path
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8031d 06h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8059d 13h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8095d 19h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8166d 19h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
788	Some of the warnings fixed.	lampret	8166d 20h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8167d 16h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
776	Updated defines.	lampret	8167d 16h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
737	Added alternative for critical path in DU.	lampret	8182d 11h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
735	Fixed async loop. Changed multiplier type for ASIC.	lampret	8185d 10h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8213d 07h	/or1k/tags/rel_14/or1200/rtl/verilog/or1200_defines.v