OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16] - Rev 216

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
196 Configuration SPRs added. simons 8347d 23h /or1k/tags/rel_16
195 New test added. simons 8347d 23h /or1k/tags/rel_16
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8348d 07h /or1k/tags/rel_16
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8348d 08h /or1k/tags/rel_16
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8348d 17h /or1k/tags/rel_16
191 Added UART jitter var to sim config chris 8349d 13h /or1k/tags/rel_16
190 Added jitter initialization chris 8349d 13h /or1k/tags/rel_16
189 fixed mode handling for tick facility chris 8349d 13h /or1k/tags/rel_16
188 fixed PIC interrupt controller chris 8349d 13h /or1k/tags/rel_16
187 minor change to clear pending exception chris 8349d 13h /or1k/tags/rel_16

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.