URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] - Rev 1778

Rev	Log message	Author	Age	Path
1155	No functional change. Only added customization for exception vectors.	lampret	7754d 01h	/or1k/tags/rel_21/or1200/rtl/verilog
1140	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.	lampret	7767d 02h	/or1k/tags/rel_21/or1200/rtl/verilog
1139	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.	lampret	7767d 02h	/or1k/tags/rel_21/or1200/rtl/verilog
1132	RFRAM defines comments updated. Altera LPM option added.	lampret	7767d 22h	/or1k/tags/rel_21/or1200/rtl/verilog
1131	Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.	lampret	7767d 22h	/or1k/tags/rel_21/or1200/rtl/verilog
1130	RFRAM type always need to be defined.	lampret	7767d 22h	/or1k/tags/rel_21/or1200/rtl/verilog
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7767d 22h	/or1k/tags/rel_21/or1200/rtl/verilog
1112	Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]	lampret	7842d 20h	/or1k/tags/rel_21/or1200/rtl/verilog
1104	Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.	lampret	7887d 14h	/or1k/tags/rel_21/or1200/rtl/verilog
1083	SB mem width fixed.	simons	7919d 09h	/or1k/tags/rel_21/or1200/rtl/verilog