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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1765

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1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7982d 22h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7983d 00h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7995d 21h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 7999d 01h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 7999d 03h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8002d 17h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8005d 17h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8034d 01h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8070d 07h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8141d 07h /or1k/tags/rel_21/or1200/rtl/verilog/or1200_defines.v

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