URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog] - Rev 663

Rev	Log message	Author	Age	Path
399	Trap insn couses break after exits ex_insn.	simons	8289d 19h	/or1k/tags/rel_21/or1200/rtl/verilog
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8292d 14h	/or1k/tags/rel_21/or1200/rtl/verilog
390	Changed instantiation name of VS RAMs.	lampret	8292d 16h	/or1k/tags/rel_21/or1200/rtl/verilog
387	Now FPGA and ASIC target are separate.	lampret	8292d 18h	/or1k/tags/rel_21/or1200/rtl/verilog
386	Fixed VS RAM instantiation - again.	lampret	8292d 18h	/or1k/tags/rel_21/or1200/rtl/verilog
370	Program counter divided to PPC and NPC.	simons	8296d 16h	/or1k/tags/rel_21/or1200/rtl/verilog
367	Changed DSR/DRR behavior and exception detection.	lampret	8297d 05h	/or1k/tags/rel_21/or1200/rtl/verilog
365	Added wb_cyc_o assignment after it was removed by accident.	lampret	8298d 00h	/or1k/tags/rel_21/or1200/rtl/verilog
360	Added OR1200_REGISTERED_INPUTS.	lampret	8299d 16h	/or1k/tags/rel_21/or1200/rtl/verilog
359	Added optional sampling of inputs.	lampret	8299d 16h	/or1k/tags/rel_21/or1200/rtl/verilog