URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog] - Rev 778

Rev	Log message	Author	Age	Path
570	Fixed order of syscall and range exceptions.	lampret	8244d 12h	/or1k/tags/rel_21/or1200/rtl/verilog
569	Default ASIC configuration does not sample WB inputs.	lampret	8244d 21h	/or1k/tags/rel_21/or1200/rtl/verilog
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8245d 00h	/or1k/tags/rel_21/or1200/rtl/verilog
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8251d 06h	/or1k/tags/rel_21/or1200/rtl/verilog
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8255d 09h	/or1k/tags/rel_21/or1200/rtl/verilog
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8255d 23h	/or1k/tags/rel_21/or1200/rtl/verilog
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8286d 02h	/or1k/tags/rel_21/or1200/rtl/verilog
401	* empty log message *	simons	8289d 12h	/or1k/tags/rel_21/or1200/rtl/verilog
400	force_dslot_fetch does not work - allways zero.	simons	8289d 12h	/or1k/tags/rel_21/or1200/rtl/verilog
399	Trap insn couses break after exits ex_insn.	simons	8289d 12h	/or1k/tags/rel_21/or1200/rtl/verilog