URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl] - Rev 1079

Rev	Log message	Author	Age	Path
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8007d 16h	/or1k/tags/rel_21/or1200/rtl
944	Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.	lampret	8009d 17h	/or1k/tags/rel_21/or1200/rtl
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	8009d 17h	/or1k/tags/rel_21/or1200/rtl
942	Delayed external access at page crossing.	lampret	8009d 17h	/or1k/tags/rel_21/or1200/rtl
916	MAC now follows software convention (signed multiply instead of unsigned).	lampret	8021d 21h	/or1k/tags/rel_21/or1200/rtl
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8038d 00h	/or1k/tags/rel_21/or1200/rtl
871	Generic flip-flop based memory macro for register file.	lampret	8074d 06h	/or1k/tags/rel_21/or1200/rtl
870	Added defines for enabling generic FF based memory macro for register file.	lampret	8074d 06h	/or1k/tags/rel_21/or1200/rtl
869	Added generic flip-flop based memory macro instantiation.	lampret	8074d 06h	/or1k/tags/rel_21/or1200/rtl
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8145d 06h	/or1k/tags/rel_21/or1200/rtl